RePP 2014: Reconciling Performance and Predictability. The RePP workshop will take place in Grenoble, France, on Sunday April 6th, 2014, as a satellite event of ETAPS 2014. The RePP workshop targets embedded systems with both efficiency requirements and critical temporal constraints, occurring in many industrial domains: avionics, automotive, railway, energy, and robotics. Guaranteeing the temporal constraints depends on the predictability properties of the whole system (processor architecture, software, OS, scheduling strategy, communications, and middleware). However, system efficiency is measured by means of average-case behavior with performance, resource utilization, and power consumption criteria. Reasons for the gap between average-case and worst-case behavior are the variation and non-determinism of the system environment, and the interferences caused by shared resources. Unfortunately, new classes of hardware platforms such as multi-core processors and multiprocessors-on-a-chip as well as the demand for adaptive and multi-mode applications quickly increase system efficiency if worst-case behavior needs to be guaranteed. The workshop will discuss approaches that attack the improvement of both worst-case predictability and of average-case performance. Topics of interest include mixed-criticality approaches, predictable (multi-core) architectures, worst-case execution time and interference analysis, resource-aware compilers, scheduling and allocation considering worst-case and average-case performance, and certification. Workshop topics Contributions should relate to the main subject of the workshop. The following issues and questions are of special interest:
- Concepts and metrics for characterizing predictability.
- Computer science has been successful in removing resource interactions from interfaces. Does it make sense to enrich interfaces with resource-related information. If yes, on which level of abstraction (instruction set, software components, …).
- Do resource interactions have an influence across abstraction layers? In particular, can improvements on one layer lead to degradation on another layer?
- Designing new hardware with special support for predictability.
- Using mainstream software development for predictability, for instance with the support of new compilers for classical programming languages.
- Multicore predictable processors: How can embedded multicore processors be designed in a time predictable fashion?
- Parallel predictable processors: How can embedded control algorithms that require a higher performance than sequential processors can deliver be parallelized and allow for time predictability of the parallel task?
- Mixed criticality: Is the execution of mixed real-time and non-real-time applications on an embedded multicore processor feasible?
- Case studies involving applications where one needs to guarantee deadlines AND average performance.
Paper submission We welcome original, unpublished, research papers on the above mentioned topics. The submission format should be in the LNCS format, between 10 and 15 pages long. The accepted papers will be printed to be handed out to the workshop participants but they will not be formally published. Instead, a follow-up call for papers will take place for LITES, the Leibniz Transactions on Embedded Systems. Submit your paper by sending the pdf to Alain.Girault@inria.fr and Thiele@ethz.ch.